When digital data is recorded on a recording medium, such as a magnetic disc or an optical disc, and reproduced from the recording medium, a reproduction waveform read from the recording medium is sampled, and a sampled value is converted into data (sampling data). Accordingly, recorded data is reproduced.
In this case, in order to reproduce data at the original sampling timing, a method, using a PLL (Phase Locked Loop), for predicting an identification point of data, generating a sampling clock corresponding to the point, and sampling a reproduction waveform is used.
In particular, for magnetic recording/reproduction, a paper titled “A PRML System for Digital Magnetic Recording” written by Roy D. Cideciyan et al. in IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 10, NO. 1, January 1992 (document 1) shows an example in which such a PLL data reproducing apparatus realizes PR4 as a PR (Partial Response).
FIG. 16 shows the PLL data reproducing apparatus. An input reproduction waveform Si is a signal having an analog waveform represented by a broken line shown in FIG. 17. According to the PLL data reproducing apparatus shown in FIG. 16, in an A/D converter circuit 61, the reproduction waveform Si is sampled in accordance with a sampling clock CLs supplied from a VCO (Voltage Controlled Oscillator) 62, and the sampled value is converted into sampling data Ds.
The sampling data Ds is equalized by a PR equalization circuit 71 formed by an FIR (Finite Impulse Response) filter, and a phase error of output data of the PR equalization circuit 71 is detected by a phase detection circuit 72. The detection result is converted, by an LPF (Low Pass Filter) 73 into data for controlling an oscillation frequency of the VCO 62.
The control data output from the LPF 73 is converted into an analog control voltage by a D/A converter circuit 63, and the oscillation frequency of the VCO 62 is controlled in accordance with the control voltage.
Thus, the phase of the sampling clock-CLs supplied from the VCO 62 is locked to the phase of the original sampling timing, which is represented by a solid line shown in FIG. 17. Accordingly, data at the original sampling timing is reproduced.
In the PLL data reproducing apparatus, however, the PLL is formed by both an analog section 60 that includes the A/D converter circuit 61, the VCO 62, and the D/A converter circuit 63 and a digital section 70 that includes the PR equalization circuit 71, the phase detection circuit 72, and the LPF 73, as shown in FIG. 16. Thus, the configuration of the system is complicated. Furthermore, since the characteristics of the VCO 62 vary depending on the temperature and the like, it is difficult to expect a stable operation.
Thus, ITR systems described in a paper titled “Interpolation in Digital Modems-Part 1: Fundamentals” written by Floyd M. Gardner in IEEE TRANSACTIONS VOL. 41, NO. 3, MARCH 1993 (document 2) and a paper titled “Interpolation in Digital Modems-Part 2: Implementation and Performance” written by Lars Erup et al. in IEEE TRANSACTIONS, VOL. 41, NO. 6, June 1993 (document 3) are proposed.
FIG. 18 shows such an ITR data reproducing apparatus. According to the ITR data reproducing apparatus, in an A/D converter circuit 81, a reproduction waveform Si is sampled in accordance with a sampling clock CLs supplied from an oscillator 82, and the sampled value is converted into sampling data Ds. The oscillator 82 is a fixed oscillator, not a VCO.
The sampling data Ds output from the A/D converter circuit 81 is supplied to an ITR section 90. The ITR section 90 forms a digital PLL by an interpolation filter 91, a PR equalization circuit 92, a phase detection circuit 93, a LPF 94, and a controller 95.
In accordance with data that is output from the controller 95 and that indicates the timing of each point Pt splitting a sampling period (sampling interval) Ts shown in FIG. 19, based on an interpolation method, which will be described below, the interpolation filter 91 outputs the value of the reproduction waveform Si at each split point (each interpolation point) Pt between adjacent sampling points Ps as interpolation data.
The data that is output from the interpolation filter 91 and that includes the interpolation data at each interpolation point Pt is equalized by the PR equalization circuit 92 including an FIR filter. Then, a phase error of the output data of the PR equalization circuit 92 is detected by the phase detection circuit 93. The detection result is filtered by the LPF 94, and captured into the controller 95.
The controller 95 updates interpolation timing in the interpolation filter 91 in accordance with the phase error of the output data of the PR equalization circuit 92. Accordingly, data at the original sampling timing is reproduced as output data of the PR equalization circuit 92, that is, as output data Do of the ITR section 90.
In the ITR data reproducing apparatus, since timing recovery can be realized only by digital processing in the ITR section 90 and the PLL is not formed by both an analog section and a digital section, the system can be configured simply. In addition, since a VCO is not used as the oscillator 82 for generating a sampling clock CLs, a stable operation can be expected.
More specifically, as a method for calculating and updating sampling timing (interpolation timing) in the controller 95, a method called an NCO (Number Controlled Oscillator) is shown in document 2 mentioned above.
In this method, in order to cause sampling timing to fit within timing defined within a sampling period Ts, updated sampling timing is subjected to integer division for the sampling period Ts, and the remainder of the division is used as sampling timing for determining a tap coefficient of the interpolation filter 91.
In addition, as an interpolation method in the interpolation filter 91, a method for obtaining an interpolation coefficient by calculating interpolation coefficients at all the timing in accordance with a sinc function in advance by using a sinc function as an interpolation function, by writing the interpolation coefficients as table values in a memory table, and by reading a corresponding table value from the memory table in accordance with interpolation timing data supplied from the interpolation filter 91 is shown in document 2 mentioned above.
In addition, linear interpolation between two adjacent sampled values is shown in document 3 mentioned above. In addition, linear approximation between two consecutive sampled values is shown in Japanese Patent No. 3255179 (document 4) (paragraph 0020 and FIG. 13).
The above-described known data reproducing method based on ITR, however, has the problems described below.
First, there is a problem with a method for calculating and updating sampling timing (interpolation timing). According to the division method shown in document 2, there is a problem not only in that the configuration of the ITR section 90 is complicated because many registers are necessary in terms of hardware but also in that the response of timing recovery is delayed because performing division reduces the processing speed.
Second, there is a problem with an interpolation method in the interpolation filter 91. If the method, which is shown in document 2, for obtaining an interpolation coefficient by writing interpolation coefficients at all the timing as table values in a memory table and by reading a corresponding table value from the memory table in accordance with interpolation timing data supplied from the controller 95 is used, an excellent reproduction output waveform with less distortion can be acquired.
In this method, however, since many table values must be prepared in a memory table, a large memory capacity is required. Thus, if the ITR section 90 is configured as an IC (integrated circuit), the chip size is increased.
In contrast, according to the methods, which are shown in documents 3 and 4, for performing linear interpolation between adjacent two sampled values, the configuration of the ITR section 90 can be simplified.
In the methods, however, since linear approximation between two sampled values is performed, there is a problem in that distortion occurs in a reproduction output waveform due to aliasing.
Thus, first, the present invention is capable of calculating and updating sampling timing at high speed with a simple configuration when data are reproduced based on ITR.
In addition, second, the present invention is capable of achieving an excellent reproduction output waveform with less distortion with a simple configuration when data are reproduced based on ITR.